One HMI reads the PLC clock and one writes it: two setups

Which tag format do the clock tags need?

BCD INT 16, on every clock field, on both panels. The format stays the same whether a panel reads the PLC clock or stages values for it, because the PLC keeps its clock as binary-coded decimal in 16-bit V-memory registers.

Changing format is the wrong first move when the display misbehaves. Format decides how a register decodes: a minute of 35 stored as BCD in V7767 displays 35 with the right tag and 53 with an unsigned-binary tag. The split between reading and writing is decided one screen earlier, at the clock source. Leave the tags alone and fix the source and the write path first.

Which V-memory locations hold the PLC clock?

Six fields live in seven reserved locations: second V7766, minute V7767, hour V7770, date V7772, month V7773 and year V7774, with V7771 between hour and date holding day of week, which the External clock configuration leaves greyed out.

The map is not consecutive: minute sits at V7767 and hour jumps to V7770. Enter each address by hand instead of auto-incrementing a block, or the hour field lands on V7768 and shows whatever that location holds. Day of week needs no tag in External; leave it unassigned on the reading panel.

How do you set up the panel that reads the time?

Select External at the top of the clock configuration, then point each clock field at its register from the table above, leaving every tag as BCD INT 16.

External tells the panel to display whatever the mapped registers hold, so the panel tracks the PLC clock field for field. The Day of Week field is greyed out in External; leave it empty and let date come from V7772. Verify each field's address by its label in the project, not by the tag name, because a project can look complete and still read date from V7771. The same source choice is the first step when you set an HMI clock from the PLC and read trend axes in time: one setting, then the fields.

How do you set up the panel that writes the time?

Select Internal, choose a Synchronize Schedule option at the bottom of the clock configuration, and point this panel's clock fields at staging V-memory of your own choosing, never at V7766 to V7774.

1. Reserve six staging locations the rest of the program never touches. In this example: V2100 second, V2101 minute, V2102 hour, V2103 date, V2104 month, V2105 year.
2. Select Internal, then pick a Synchronize Schedule option at the bottom of the clock configuration. The panel writes its clock values into the staging block on that schedule.
3. Assign the panel's clock fields to the staging locations, tags still BCD INT 16.
4. In the PLC program, add a rung with the TIME instruction to load the staged hour, minute and second, and a rung with the DATE instruction to load the staged year, month and date. The manual prints each instruction's operand order.
5. Execute the two rungs once, after the staging values arrive, from a pushbutton bit the panel writes or from a maintenance switch.

The system time and date V-memory is the PLC's clock storage, and the TIME and DATE instructions are its write path. Route the panel's writes through staging, and let the ladder set the clock. This is the same instruction path you follow to set a PLC clock from the operator panel for daylight saving time: values land in ordinary V-memory, then the instructions apply them.

What does a worked example look like with real values?

At 16:35:07 on the 25th, the reading panel shows 16:35:07, second V7766 holds BCD 07, minute V7767 holds BCD 35, hour V7770 holds BCD 16 and date V7772 holds BCD 25, and a tag misread as plain binary turns that minute into 53.

BCD packs each decimal digit into four bits, so minute 35 sits in V7767 as hex 0x35. An unsigned-binary tag computes 3 × 16 + 5 = 53. Hour 16 sits as 0x16, which computes 1 × 16 + 6 = 22, so the display reads 22:53:07. Second 07 is 0x07 either way, so every field below 10 looks right and a format fault hides for the first part of each hour, returning the moment the minute passes 09.

On the write side, the Internal panel pushes its clock into V2100 to V2105 on its schedule. The TIME rung loads 16, 35 and 07; the DATE rung loads the year, the month and 25. The PLC clock jumps to those values, V7766 resumes climbing by 1 each second, and the reading panel shows the new time on its next poll.

How do you tell a wrong format from a wrong address?

A wrong format garbles values above 9 in a predictable way: minute 35 displays as 53 and hour 16 as 22; a wrong address shows a plausible but wrong field, like a date that never climbs past 7 because it reads day of week.

Put all seven registers in one data view, the same view you would use to monitor multiple PLC timer values in one data view. If V7766 climbs by 1 every second, the PLC clock runs and the fault is at the panel; registers sitting still point at the PLC clock or the link. Then read the signature. Garbled values above 9 mean format. A date capped between 1 and 7 means the date field points one register low, at V7771, day of week.

Why does the panel blank and show 12:00 AM?

The panel restarted. A blank screen or a clock showing 12:00 AM during an update tells you the panel's own display and clock reset, and it tells you nothing about the PLC clock, which keeps running in V7766 to V7774.

The restart came from the panel project or its download, and the PLC clock counted straight through it. After the panel returns, re-check the two paths separately: the reading panel should track V7766, and a successful write appears first in the staging block, then in the clock registers. Judge the write by what lands in the PLC, never by the writing panel's screen.

Should the two jobs stay on two panels?

Yes, when both panels are permanent operators on the machine: keep reading on one panel with External and writing on the other with Internal, because one mode per panel is a clean split and the staging write path lives in one project.

With one panel only, select External for the display and set the clock from the ladder through the same staging rungs, or from the programming software. With several PLCs that must agree, synchronize multiple PLC clocks from one master and leave every panel in External as a reader. Where the PLC accepts a network time server as its clock source, use it: the clock sets itself and both panels become readers.

Recommendation: keep both clock tags at BCD INT 16 on both panels, put the reading panel in External on second V7766 through year V7774, and put the writing panel in Internal with a Synchronize Schedule into staging V-memory the TIME and DATE instructions consume. Stop changing tag formats: the split lives in the clock mode and the write path, and the format was right from the start.

Questions