Set the PLC clock from the panel by writing the six date and time registers as 16-bit BCD. Verify the format with a 59-minute entry that reads 0x0059 in hex, and write a constant between 0 and 6 for day of week when no logic reads the weekday.
When daylight saving time starts or ends, the operator walks to the panel, corrects the hour, and the PLC clock follows. The setup behind that is mostly one decision: the six date and time numeric-entry tags must be defined as 16-bit BCD, because the panel writes each entry in whatever format its tag declares and the PLC clock registers hold BCD. Check the format on the bench with a minute entry of 59. The register reads 0x0059 with BCD tags and 0x003B with plain binary tags. If no logic reads the day-of-week register, a legal constant between 0 and 6 satisfies the clock instruction's range check. This article sets up both sync paths, lists what each symptom after a write points to, and gives the bench test to run before the panel ships.
The six clock registers and the format they hold
The real-time clock in this write path lives in six 16-bit word registers: year, month, day, hour, minute and second, one field per word. Each field is stored as BCD, one decimal digit per 4-bit nibble, so a minute of 47 sits in the word as 0x0047. The DATE and TIME instructions read those nibbles as decimal digits, not as a binary number.
The panel never guesses the format. It writes each numeric entry in the format its tag declares, so the tag format decides everything. Set all six tags to 16-bit BCD; one panel editor lists the type as BCD_INT_16. With BCD tags the values land in the registers ready for the clock instruction, and the ladder converts nothing.
The wrong fix first is plain 16-bit integer tags. Enter 12 and the register receives 0x000C, and a BCD reader meets the digit C in a field that only holds decimal digits, so the value comes out as garbage or the write is rejected. That mismatch is the same failure behind an HMI panel showing nonsense numbers from a PLC BCD analog register.
One entry needs a look before you wire the screen: the year word. Some clock instructions take a two-digit year and some take four digits, so read the register table in the CPU manual and size that one field to match.
Pick the sync direction in the panel editor
Panel editors that support clock sync keep the setting in the project setup; one editor puts it on a Clock tab under Setup > Project Attributes. The setting has two directions. Internal means the PLC follows the panel clock. External means the panel follows the PLC clock. For this job pick Internal, and put the PLC clock registers into the editor's time tag list so the panel can display PLC time next to its own.
The wrong fix first is correcting the panel clock while the direction is still External. The panel re-syncs from the PLC on the next cycle and the operator's correction disappears.
When the editor offers no clock sync your CPU can use, or you want to control the exact moment the clock changes, use the button handshake in the next section. The handshake is also the pattern for any other operator-entered PLC value, such as letting an HMI change a PLC timer preset.
Apply the write with a momentary button when there is no direct sync
Build the screen from top to bottom: a display field with the panel time, a read-only field with the PLC time, the six read/write numeric-entry fields, and a momentary push button that sets one bit in the PLC. The display side of the read-only PLC time field uses the same clock-register read the rest of this setup uses; the write is the new part.
The ladder behind the button bit runs four steps in order:
- Range-check each entry word before anything moves: month 1 to 12, day 1 to 31, hour 0 to 23, minute 0 to 59, second 0 to 59. A bad entry stops here and never reaches the clock.
- Pack the fields into the word layout the DATE and TIME instructions take: shift each field into its bit positions and OR the words together (SHRL and OR in the instruction mnemonics this write path was documented with).
- Execute the DATE and TIME instructions.
- Copy the applied words into comparison registers and reset the button bit.
Two triggers are worth having. A once-per-minute comparison of the entry words against the applied copies catches a correction even if the button press is missed. The button bit also keeps a half-typed entry from landing, because the write happens on the press, never on the field edit.
A screen whose only job is showing the line shift schedules or andon notices runs its own content and never writes to a PLC. That is shop-floor signage, a separate job from this panel write.
What each symptom after a write points to
- The register shows a hex digit above 9 (A to F) in a time field. Binary was written into a BCD field. Set the tag format to 16-bit BCD and repeat the write.
- A fixed pattern shift, for example 12 entered and 18 displayed. A BCD word was read as a binary number. Make the tag format and the reader agree on BCD.
- The clock never changes. The apply logic never fired: the button bit never set, an entry failed the range check, or the sync direction points the wrong way.
- The operator's correction vanishes within a minute. The editor is set with the panel following the PLC. Switch the direction so the PLC follows the panel.
- The time lands correctly and the weekday is wrong. The day-of-week register was never written or was seeded wrong. See the next section.
Day of week: a legal constant and when it matters
If no logic reads the weekday, the DATE and TIME instructions run fine without it. The CPU range-checks each field, seconds 0 to 59 and the like, and lets a weekday that disagrees with the calendar pass. Write a constant between 0 and 6 into the day-of-week register so the range check passes, and watch that per-field behavior on your CPU the first time the apply logic runs.
If any logic reads the weekday register, do not write a dummy value from the panel. That register runs its own count from 0 through 6, seeded once and stepping with the clock, so it follows the ticks and wraps to 0, not to the calendar. A wrong seed stays wrong through every seasonal correction until someone sets it from the programming software. Vendor clock-sync example programs often refuse to run when the weekday register is in use, for the same reason. In that case set the date and time from the programming software, or compute the weekday from the date in ladder logic. The calculation is a known formula, but it rarely earns its keep in ladder.
Example: a 59-minute entry read back in hex
The inputs: a test value of 59 typed into the panel's minute entry field; one 16-bit word register for minutes, read back in hexadecimal from the programming software; two candidate tag formats, 16-bit BCD and plain 16-bit binary. All three come from the write path set up above, and the hex readings are arithmetic.
The rule in words: binary stores the number's value across the whole word. BCD stores each decimal digit in its own 4-bit nibble. Reading the word in hex separates the two whenever a digit is above 9.
The arithmetic. Binary: 59 = 3 × 16 + 11, so the word reads 0x003B. BCD: the 5 packs into nibble 0101 and the 9 into nibble 1001, giving 0000 0000 0101 1001, displayed as 0x0059. Read as a binary number that word is 5 × 16 + 9 = 89.
The result: 0x0059 means the tag wrote BCD and the setup is right. 0x003B means the tag wrote binary; change the tag format to 16-bit BCD and run the same entry again until the register reads 0x0059.
The decision and its threshold: any hex digit above 9 in a time field means binary was written into a BCD field, so fix the tag format. A register whose digits match what the operator typed means BCD, and the setup ships.
Use 59 and not a small number. Below 10 the two formats read identically, since 9 minutes is 0x0009 either way. The bench shortcut of flagging a lowest nibble with bits 3 and 2 both set catches only digits 12 to 15; digits 10 (1010) and 11 (1011) are also illegal BCD and pass that bit test, and binary 59 itself ends in nibble 11. Read the hex value; skip the bit test.
Bench-test on a spare CPU before the panel ships
An identical CPU without a panel still covers the ladder. Drive the six clock registers by hand from the programming software, execute the DATE and TIME instructions, and watch the clock take each value: hour 23, minute 59, month 12, day 31, then month 13 and watch the range check stop it. Attach the panel afterwards and run the 59-minute entry from the example above; the register should read 0x0059.
Rehearse the seasonal correction too. Set the panel clock forward one hour, apply, and check that every time-based output in the program lands where the corrected clock says it should.
One safety point: if the clock triggers chemical dosing, batching or shutdown schedules, a one-hour correction moves every one of those events by one hour. Make the correction in a window when those outputs are idle, or check that each schedule tolerates the shift.
Recommendation: Define all six numeric-entry tags as 16-bit BCD, set the editor's clock sync so the PLC follows the panel, and fall back to the momentary-button handshake when direct sync is unavailable. Check the tag format on the bench with a 59-minute entry; the register must read 0x0059 in hex, so change the tag format and rerun until it does. Write a constant between 0 and 6 into day of week only when no logic reads the weekday register, and make the seasonal correction in an idle window whenever the process runs on time-based schedules.
Questions
What does the operator actually change for daylight saving time?
One hour on the hour field, nothing else. In the United States, clocks spring forward on the second Sunday in March and fall back on the first Sunday in November. The operator enters the corrected hour at the panel and presses the same apply button used for any other correction, and the write path is identical. Where the panel editor has direct clock sync with the PLC following the panel, the PLC clock moves the moment the panel clock is set.
Why did 12 show up in the PLC as 18?
Because the register holds 0x0012. A tag defined as 16-bit BCD stores the two decimal digits one per nibble, and 0x0012 read as a plain binary number is 1 × 16 + 2 = 18. Writer and reader disagreed about the format: BCD on one side, binary on the other. Set the tag format to match the format the clock instruction reads, and the same entry lands as 12.
Does this change if the PLC stores its clock in binary instead of BCD?
Some CPUs keep their clock fields as plain binary words, and the same 59-minute test still separates the formats: a binary clock register reads 0x003B hex where a BCD register reads 0x0059. Check the register format table for the clock instruction in your CPU manual, then set the tag format to match it. The rule is the same either way. The tag format and the register format must agree, so the seasonal correction converts nothing in the ladder.
Planning information, not legal or engineering advice. Rules differ by place: check codes and permits with your local authority and your licensed trades.