Accumulating timer presets across two V-memory registers

How do you time more than 999.9 seconds on one timer?

You switch the rung to the TMRA accumulating timer. Its preset lives in two consecutive V-memory registers instead of one, so the interval ceiling rises from 999.9 seconds to eight BCD digits. At the 0.1-second count step that reaches about 115.7 days.

The ordinary timer counts in 0.1-second steps and reads its preset from a single register. Four BCD digits, at most 9,999 counts, set the ceiling you are hitting. The accumulating instruction reads its preset as a double word, eight digits, and the same count step carries it to 99,999,999 counts at full scale. Its behavior differs too: the elapsed count holds when the rung's input drops, and it clears only when the program resets it. The reset rung is part of this job, not an afterthought.

What do you need before you change the program?

You need the program open in DirectSoft5, two consecutive V-memory registers with nothing else stored in them, two consecutive timer elements that no other rung uses, and, when operators set the interval from a panel, an HMI numeric object that writes a 32-bit BCD value.

Gather these before you touch the rung:

• The rung to change, with its input contact, timer number, done output and current preset noted.
• A free register pair and a free element pair, both checked against the whole program (the next two sections show how).
• The processor's user manual, for the TMRA operand rules and the retentive-memory settings.
• The move instruction that loads the value: the 32-bit double-word move, OUTD in this software.
• Download access, so the changed rung goes in from programming mode under your control.

Which V-memory registers does the TMRA preset occupy?

The instruction takes one address as its operand and uses that register plus the next consecutive one. A preset entered as V1400 occupies V1400 and V1401, and the second address never appears anywhere in the program.

That pairing is what makes the two-register idea work. An ordinary timer pointed at the first of two words gains nothing, because its operand still references a single location and the extra digits in the neighbor are invisible to it. TMRA treats the pair as one double word, so both registers belong to the timer. Reserve them the way you would reserve a block in an HMI memory map: named, written from exactly one source, out of bounds for every other rung. If the words held other data before the change, clear them first; the FILL instruction clears a V-memory range in one rung. A double word is the right width for this preset. A PLC hour compare that stays in a single word is the reminder that each value in the program gets its own width decision.

Which timer elements does TMRA need free?

A TMRA consumes two timer elements: the number you assign plus the next consecutive one. A timer on T5 also takes T6, and that number has to stay out of every other rung in the program.

Check the neighbor before you commit the assignment. Search the project for the element that follows the one you want, and move your choice if anything else claims it. Using even numbers for the accumulating timers is a habit that keeps the pairing visible, and the project search is the check that actually settles it. The register pair and the element pair are two separate reservations, so run both checks one after the other.

How do you write the preset so the timer reads it as BCD?

The preset pair holds binary-coded decimal, so the value moved in must be a BCD double word. A binary write of 864,000 leaves the pattern 0x000D2F00, whose digits D and F are no decimal digits, so the timer runs on a value that was never a number.

In BCD each decimal digit occupies four bits, so 864,000 stores as the eight digits 00864000, the bit pattern 0x00864000 across the pair. The example below carries this same value through the whole job. Set the writing side to BCD before anything touches the registers: the data-format setting behind a timer preset decides the same thing in single registers, and the binary-versus-BCD mix-up that breaks a preset multiply after 9 is the same trap with smaller numbers. After the first write, compare the raw pair against the pattern the example computes. A value that looks right on the panel can still land in the registers in the wrong representation. When a long accumulating preset miscounts after a format change, a DL05 write-up traces the fault to exactly this BCD mismatch.

What does an example calculation for a 24-hour preset look like?

A curing tank needs one full 24-hour hold between resets: 24 h is 86,400 s, the 0.1-second count step turns that into 864,000 counts, and 864,000 sits well inside the eight-digit range of the pair.

The arithmetic, start to finish:

• Seconds: 24 h x 3,600 s/h = 86,400 s.
• Counts: 86,400 s / 0.1 s per count = 864,000 counts.
• Range: eight BCD digits top out at 99,999,999 counts, so 864,000 fills less than one percent of the pair.
• Storage: the BCD double word 0x00864000, placed into V1400 and V1401 with one double-word move.
• Elements: the timer on T5, with T6 reserved and unused.
• Runtime: input on, elapsed count climbing, done output on at 864,000, program reset to zero for the next hold.

One pattern decides the whole job. 0x00864000 in the pair runs the hold for exactly 24 hours, while the binary form parks two non-decimal digits in decimal places and the hold ends wherever that misread value lands.

How do you set the 24-hour preset up, step by step?

You replace the rung's timer instruction with TMRA, reserve the register pair and the element pair, load the BCD preset, add the program reset, and download in programming mode with the machine in a safe state.

1. Open the rung and note what it does today: input contact, timer number, done output, current preset.
2. Change the instruction to TMRA and keep the same input contact and done output, so the machine logic reads the same after the change.
3. Assign a timer number whose next consecutive element is free. A TMRA on T5 claims T6, so reserve T6 and leave it unused in every rung.
4. Enter the preset operand as the first register only: V1400. V1401 is part of the preset now and belongs to the timer.
5. Load the value. An initialization rung with one OUTD move places the BCD double word in both registers. For operator entry, point an HMI numeric object at the timer preset address with a 32-bit BCD format, one address per preset, the rule an EA1-S3ML-N panel note spells out for timer presets.
6. Add the reset rung. The accumulating timer holds its elapsed count until the program clears it, so reset the element on the rung that ends the cycle or starts the next one.
7. Save the program and download it from programming mode, with the machine in a safe state. A preset change landing on a running line can start or stop equipment while people are working at it.

How do you check that the timer took the new preset?

Monitor the register pair, run one shortened cycle, and watch three things: the pair shows the BCD pattern 00864000, the elapsed count climbs while the input is on and holds when it drops, and the done output comes on exactly at the preset.

Load a test value first so the proof takes a minute instead of a day. 600 counts at the 0.1-second step is a 60.0-second interval, long enough to watch the done output and the reset, short enough to wait out at the bench. Then the symptom split:

• The panel shows the new value and the pair stays where it was: the write path is wrong, starting with the object's address and format.
• The pair changes and the interval comes out wrong: the value landed in binary, or the operand points at the wrong register.
• Done fires and the next cycle starts part-way through: the reset rung is missing or does not cover the element pair.

Recommendation: When an interval outgrows a single register, move the rung to TMRA on a free consecutive element pair, enter only the first V-memory register as the preset operand, write the value as a 32-bit BCD double word, reserve both registers and both elements, and put the reset in the program. Then prove the cycle with a short test preset before the first real interval runs.

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