One internal bit that an OUT coil drives in one rung and a reset clears in another lets a machine advance before its permissive input makes, because the OUT rewrites the bit every scan and the clear cannot hold. Replace the OUT with a SET of the same bit, keep exactly one SET and one reset per sequence bit, and retest the event order that failed first.
An output that energizes before its permissive input is true is usually a logic fault, not a sensor fault. When one rung writes a sequence bit with an OUT coil and a later rung clears the same bit with a reset, the OUT rewrites the bit on every scan and the clear cannot hold. The machine then advances a step early. The repair is to write the bit as a SET and reset pair: SET where the sequence earns the state, reset where it clears, and no third write to that address anywhere in the program. This page works through a bottle case packer whose drop output Y401 fired as soon as the full-grid switch X101 made, before the case-present switch X104, and shows the scan trace, the one-rung change and the test order that verifies the repair.
Why the output fires early
A PLC solves its ladder the same way every scan: rungs in ascending rung order, contacts left to right inside each rung, once per processor pass. A small machine PLC typically completes a pass in 1 to 10 ms, so every rung executes 100 to 1000 times a second.
The instruction type decides what a write does. An OUT coil writes its rung's condition into its bit on every scan: the bit is ON while the rung is true and OFF while the rung is false. A reset instruction behaves as its instruction set documentation states: it turns the bit OFF when its rung is true, and the bit stays OFF after the rung goes false. With two rungs writing one bit using different instruction types, the state the bit carries at any instant depends on which write executed last in that scan.
On this machine the drop output Y401 sits in rung 25 and is meant to wait for X104, the case-present switch. Rung 23 wrote the sequence bit C31 with an OUT coil and rung 31 reset C31. With that pair in the program, Y401 came on the moment the full-grid switch X101 made, with no case under the grid. Changing rung 23 to SET C31, with the rung-31 reset kept, gave the intended order. Putting the OUT back reproduced the fault on the next run, which pins the cause on the write scheme rather than on any sensor.
Contact order inside a rung never outranks rung order across the program: a rung's branches combine before the rung writes its output, so adding the X104 contact ahead of Y401 could not beat the earlier write from rung 23. How PLC rung branches combine before the output is written covers that side of the rule. A bit decided by write order is the same race that decides who wins the write when two HMIs write to one PLC.
Symptoms and what each one points to
- The output fires the moment an upstream switch makes. Y401 energized as X101, the full-grid switch, made while X104 was still open. The state the output rung reads was already written, so the switches are not the first thing to check.
- Adding the permissive contact changes nothing. The X104 contact went in ahead of the output here and the fault stayed. When a contact you know is open still lets the output fire, the rung is reading a bit that another rung rewrites; follow the bit.
- One bad drop, then a dead machine. The drop happens with no case underneath, the cycle stops, and the case arriving later starts nothing because the sequence never sees the state change it was waiting for.
- The input LEDs look perfect. Tripping each sensor lit its input LED here, and that only tells you the input card sees the switches; it says nothing about which rung wrote which bit.
- Timers look guilty and are not. Two timers in this program, T4 and T5, shared one preset value. A preset sets a duration; it sets no order of operations. Leave presets untouched until the bit writes are right.
Checks before you change the rung
A sequence fault on a case packer drops bottles into a grid with no case under it, and a forced output can move the grid head. Stop the cycle and put the machine in its safe state before you edit, force or download logic, and run any live test under the machine's approved safe test procedure. Do not force Y401 on or bypass the case-present input to keep production moving.
- Record the starting point. Save a copy of the project and note the original logic in the rungs involved: 23, 25 and 31 here. The rung comments at the top of the program carry the intended sequence; write it in one sentence, here: Y401 stays OFF until X104 is true.
- Cross-reference the bit. Type the address C31 into the programming software's cross-reference or usage list. The list shows every rung that reads or writes the bit and the instruction type at each hit. A sequence bit should show exactly two writes, one SET and one reset.
- Watch one failing cycle. With the machine safe, put C31, Y401, X101 and X104 on the monitoring view and note which rung and which transition first energize the output.
The fix: one SET, one reset, no third write
- Open the rung that latches the bit, rung 23 here, and confirm its destination is C31.
- Change the OUT instruction on C31 to a SET. Keep the rung's contacts and conditions exactly as they are.
- Open the rung that clears the bit, rung 31 here, and confirm the reset of C31 and its condition are unchanged.
- Run the cross-reference on C31 again. It must now show one SET and one reset and nothing else.
- Download through your site's change procedure and change nothing else in the same download: no presets, no contacts, no timers. One change per test is what makes the retest attributable.
The change holds because a SET writes the bit only while its rung is true and leaves it alone when the rung goes false, so the reset's clear survives between scans. The pair behaves like a latch: ON when the sequence earns the state, OFF when the clearing rung says so.
Recommendation: when a machine advances a step before its permissive and the cross-reference shows an OUT coil plus a reset on the same internal bit, change the OUT to a SET of that bit and leave the reset where it is. Keep exactly one SET and one reset per sequence bit, and retest the event order that failed before accepting a cycle that passed.
Example: tracing C31 through one scan with an OUT in rung 23 and a reset in rung 31
Inputs, with their sources:
- C31, the sequence bit, driven by an OUT coil in rung 23 and cleared by a reset in rung 31 (the program under repair).
- Y401, the drop output in rung 25, required to stay OFF until X104, the case-present switch, is true (the intended sequence).
- X101, the full-grid switch, whose state makes the grid-full condition in rung 23 (the machine's inputs).
- 1 to 10 ms per scan, the typical pass time for a small machine PLC (typical published range for compact controllers).
The rule in words: the processor solves rungs in ascending order once per scan; an OUT writes its rung's condition to its bit every scan; a reset clears its bit when its rung is true and the bit stays OFF afterwards; a later rung reads what earlier rungs wrote in that same scan.
| Order in the scan | Rung | Instruction | What it writes |
|---|---|---|---|
| First | 23 | OUT C31 | Grid-full condition true, so C31 is written ON |
| Second | 25 | OUT Y401 | Executes with C31 already ON, so Y401 is driven ON |
| Third | 31 | RST C31 | C31 cleared, but Y401 has already fired in this scan |
The arithmetic: 1 s ÷ 10 ms = 100 scans a second, and 1 s ÷ 1 ms = 1000 scans a second, so the OUT rewrites C31 between 100 and 1000 times a second. The reset's clear, whenever the OUT rung is true, survives less than one full scan, under 10 ms at the slow end. Two writes of different types on one bit, every scan, mean the bit's state is set by write order.
Result: with the grid full and no case at X104, Y401 came ON, the trip opened, the bottles dropped into the fingers and the cycle stopped, and the case arriving later started nothing. That is the failure as it ran. It also explains the other half of the behavior: with a case already present before the grid filled, C31 was legitimately ON, so the same writes did no harm. After rung 23 became SET C31 with the rung-31 reset kept, the machine cycled as intended, and restoring the OUT brought the early fire back on the next run.
Decision: the threshold is one pair. A cross-reference that shows an OUT and a reset on one internal bit is reason to change the OUT to a SET of the same bit before you check sensors, timers or wiring.
Test the order that failed first
The fault lives in one event order only: the grid fills before the case arrives. A cycle with the case already present runs correctly on either version of the logic, so a clean case-first run tells you nothing about the write scheme. Run the late-case order first.
- Put X101, X104, C31 and Y401 on the monitoring view, with the machine in its approved test mode and the area clear.
- Run a controlled cycle in which the case-present switch makes after the grid-full switch, if the safe test procedure allows that order.
- Confirm Y401 stays OFF until X104 is true and that the machine resumes the cycle when the case arrives.
- Repeat the normal order, case before the grid fills, to confirm it still runs.
If the safe procedure cannot produce a late case without risking a dropped load, run the order in the machine's approved simulation or maintenance mode. Do not bypass the case-present input to stage the test.
If the early fire comes back
The revert test above settles the write scheme as the cause: OUT back in, fault back; SET in, fault gone. If the early fire returns after the repair, take this list in order.
- Cross-reference the bit again; a third writer may have appeared. Operator panels write PLC memory too, and an alarm acknowledgment that sets a PLC bit is one routine panel write. Clearing a coil range when the panel returns to a screen is another way a screen write lands behind the ladder.
- Compare each input bit with its switch. Operate X104 by hand and watch its bit follow in the data view; a case-present switch that trips early or sticks ON satisfies the permissive ahead of the case.
- Check the I/O commons against the machine's electrical drawing. A floating common on an input or output card produces behavior that looks like logic nobody wrote.
- Open the timers last. T4 and T5 shared one preset here and that was never the fault. Presets set durations; look at them only if the corrected sequence still runs with the wrong timing.
Questions
How do I find every rung that writes a bit in the program?
Use the cross-reference or usage list in the programming software. Type the bit address, C31 in this program, and the list shows every rung that reads or writes it together with the instruction type at each hit. Read the types before you judge the logic: two writes of the same type can be intentional, while an OUT together with a SET or a reset on one bit is the combination that breaks a sequence. Run the same search on each output address, in case the output is driven from more than one rung.
Should the matching timer presets have been changed as part of the fix?
No. The two timers in this program, T4 and T5, shared one preset value, and the fault appeared and cleared with no preset touched, so the presets were not the cause. A preset sets a duration only; the order of operations comes from the bit writes. Open the timers only if the corrected bit logic still leaves the cycle with the wrong timing, and then compare each timer's rung condition and elapsed value against the step it is meant to time.
Why does a SET hold the bit when an OUT does not?
A SET instruction writes the bit ON only while its rung is true and leaves the bit alone when the rung goes false, so the clear from the reset rung survives between scans. An OUT rewrites the bit on every scan, ON while its rung is true and OFF when it is false, so any clear gets overwritten on the next pass. The pair of one SET and one reset behaves like a latch, and the bit stops depending on which rung executed last.
Planning information, not legal or engineering advice. Rules differ by place: check codes and permits with your local authority and your licensed trades.