Display a PLC countdown timer on an HMI panel

The accumulated value counts the wrong way for a countdown

A PLC timer measures elapsed time. Start it, and the accumulated value climbs from 0 toward the preset; on an 8-minute test it climbs from 0 to 4800 counts on a 0.1-second base. Put that register on the panel and the operator watches a count-up that finishes exactly when the test does, which is backwards for a wait.

Remaining time is the mirror: how much of the preset is left. No timer instruction hands that value over, so the rung computes it every scan: preset minus accumulated, stored in a register of its own.

The accumulated value is still the right source when the panel should show elapsed time; that display case carries its own scaling and is covered in show a timer counting from a PLC current value. For a countdown, compute a new register.

Three registers and one subtraction

Two rungs do the whole job. One runs the timer while the test is in progress; the other does the subtraction and writes the result where the panel reads it.

The example uses these operand names; map each to the matching tag or address in your project:

• C0: the test-in-progress state bit
• T0: the test timer, 0.1-second time base
• K4800: the timer preset, in 0.1-second counts
• TA0: the accumulated value of T0
• V2000: a free holding register the panel reads

Rung 1: with C0 on, time T0 to the K4800 preset.

Rung 2: with C0 on and T0 short of preset, load K4800, subtract TA0, and store the result in V2000.

The panel reads V2000 and never TA0. Some platforms ship a down-counter instruction that performs this subtraction inside the timer itself; the Logix5000 countdown timer for a time-remaining display covers one, and on a plain count-up timer the two-rung pattern above is the whole fix.

Keep the preset and the accumulated value in one time base

Counts are seconds divided by the time base, so a preset is arithmetic before it is a constant. Eight minutes works out to 4800 counts on a 0.1-second base, 480 counts on a 1-second base and 480,000 counts on a millisecond base. A preset borrowed from a project with a different base is off by a factor of 10 one way or 100 the other.

Inside one timer instruction, preset and accumulated value share the base, so the subtraction is sound in counts end to end. The panel translates for display: a numeric object with a scaling constant set to divide by 10 turns a 0.1-second register into whole seconds.

Check the base before trusting the readout. With the timer timing, watch the accumulated value for 10 seconds: a 0.1-second base adds 100 counts, a 1-second base adds 10, a millisecond base adds 10,000. Divide whatever it added by 10 and you have the rate the countdown should fall at, in counts per second.

Example: an 8-minute countdown on a 0.1-second timer

The inputs, and where each comes from:

The operand names are this example rung's own; keep your project's names for the same four roles.

The rule in words: while the test runs and the timer has not reached preset, remaining counts = preset − accumulated, written to V2000.

The arithmetic, at 3 min 20 s into the test:

• Elapsed time is 200 s, so TA0 = 200 s ÷ 0.1 s per count = 2000 counts.
• V2000 = 4800 − 2000 = 2800 counts.
• 2800 counts × 0.1 s = 280 s, shown on the panel as 280 seconds with the divide-by-10 scale, or 4 min 40 s with a minutes-and-seconds format.

At expiry: TA0 = 4800, so V2000 = 4800 − 4800 = 0 counts, and the panel reads 0:00.

The decision this example hands you: mid-test, V2000 must sit between 0 and 4800 and fall at 10 counts per second on this base. A value above 4800, a wrapped or negative-looking value, or one that holds still while the test runs points at the time base, the gating or the register address, in that order.

Point the numeric object at the computed register

The panel object needs four things set:

• Source: V2000, the computed register. TA0 on the panel gives the count-up covered above.
• Format: the same interpretation the PLC writes; this example stores BCD. An object set to another interpretation turns a healthy register into impossible digits, a fault covered in HMI shows nonsense numbers from a PLC BCD analog register.
• Scale: divide by 10 to show whole seconds on a 0.1-second register.
• Digits: the 4800-count range needs four digits, so a four-digit object covers the full run from 4800 down to 0.

A minutes-and-seconds readout such as 4:40 is a formatting choice on the object; formatting a PLC timer duration display shows how to split counts into minutes and seconds.

What the display shows at idle, mid-test and expiry

Three states, three values:

• Idle, C0 off. The timer rung drops out and the timer resets its accumulated value to 0. A third branch, enabled while C0 is off, moves the preset into V2000, so the panel shows the full 8 minutes between tests.
• Test running. The subtract rung writes V2000 every scan and the display falls 10 counts per second.
• Time expired, test still on. The inverted done-bit contact opens, the subtract rung stops writing, and V2000 keeps the last value written, which is 0. The panel holds 0:00, and the gate keeps the register from ever holding a below-zero result if the test runs past 8 minutes.

The idle move and the counting subtract sit on opposite states of C0, so exactly one of them writes V2000 in any scan. When several rungs can write one register, scan order decides which value survives; the page PLC rung branches combine before the output is written walks through that mechanism.

An abort takes the same path: C0 off mid-test resets T0, the idle branch restores the preset, and the panel is back to the full 8 minutes for the next run.

When the operator sets the test length from the panel

Point the subtraction at the register the panel writes the preset into, and the countdown follows edits with no change to the rung: the panel writes the new value, the subtract rung reads it back, and V2000 recalculates on the next scan. The write path is the subject of let an HMI change a PLC timer preset instead of a constant, and enforcing increment and decrement value limits in PLC logic keeps the operator inside the range the test allows.

Recompute every scan while the test runs. A remaining-time value captured once at the start keeps counting to the old length after an edit; a per-scan subtract shows the new preset minus the time already spent, which is the honest number.

The pattern is the same across the PLC-to-panel cases on this site; the rest of them sit under shop-floor screens.

Recommendation: compute the countdown in the PLC as preset minus accumulated into a third register, both operands in the timer's own time base. Gate the subtract rung with the test bit and the inverted done bit, add the idle branch that restores the preset when the test is off, and read the register on the panel as 0.1-second counts with a divide-by-10 scale for whole seconds. Use a native down-counter instruction only where the platform ships one.

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